Register Writes And Effective Latency - Analog Devices ADSP-BF506F Hardware Reference Manual

SPORT Registers
Table 19-5. SPORT Register Mapping (Cont'd)
Register Name
SPORT_MCM2
SPORT_MRCSn
SPORT_MTCSn
SPORT_CHNL

Register Writes and Effective Latency

When the SPORT is disabled (
writes are internally completed at the end of the
occurred, and the register reads back the newly-written value on the next
cycle.
When the SPORT is enabled to transmit (
corresponding SPORT configuration register writes are disabled (except
for
SPORT_RCLKDIV
registers). The
, and
SPORT_CHNL
After a write to a SPORT register, while the SPORT is disabled, any
changes to the control and mode bits generally take effect when the
SPORT is re-enabled.

Most configuration registers can only be changed while the
SPORT is disabled (
SPORT is re-enabled. The only exceptions to this rule are the
TCLKDIV
19-46
Function
Secondary multichannel
mode configuration register
Receive channel selection registers
Transmit channel selection registers Select or deselect channels in a mul-
Currently serviced channel
in a multichannel frame
TSPEN
,
SPORT_TCLKDIV
register writes are always enabled;
SPORT_TX
are read-only registers.
SPORT_STAT
/
TSPEN
/ registers and multichannel select registers.
RCLKDIV
ADSP-BF50x Blackfin Processor Hardware Reference
Notes
Configure this register before
enabling the SPORT
Select or deselect channels in a mul-
tichannel frame
tichannel frame
and cleared), SPORT register
RSPEN
SCLK
set) or receive (
TSPEN
, and multichannel mode channel select
= 0). Changes take effect after the
RSPEN
cycle in which they
set),
RSPEN
,
SPORT_RX