Rsi Data Counter Register (Rsi_Data_Cnt) - Analog Devices ADSP-BF506F Hardware Reference Manual

RSI Registers
Table 21-18. RSI_DATA_CONTROL Register (Cont'd)
Bit Name
9 CEATA_CCS_EN
15:10 Reserved

RSI Data Counter Register (RSI_DATA_CNT)

The
RSI_DATA_CNT
when the data path state machine becomes enabled and moves from the
IDLE state to the WAIT_S or WAIT_R states. As the data is transferred,
the counter decrements; upon decrementing to zero, the state machine
then moves back to the IDLE state and the
register is set.
RSI Data Counter Register (RSI_DATA_CNT)
Read
15 14 13 12 11 10
0xFFC0 3830
0
0
DATA_COUNT
Figure 21-15. RSI Data Counter Register
Table 21-19. RSI_DATA_CNT Register
Bit Name
15:0 DATA_COUNT
21-64
Function
Command completion signal
enable
0 = Disabled
1 = Enabled (wait for command
completion signal)
Reserved
register is loaded from the
9 8 7 6
0 0 0
0 0 0 0 0
Function
Number of bytes still to be trans-
ferred
ADSP-BF50x Blackfin Processor Hardware Reference
RSI_DATA_LGTH
flag of the
DAT_END
5 4 3 2 1 0
0 0
0 0 0 0
Type Default
R/W 0
R/W 0
register
RSI_STATUS
Reset = 0x0000
Type Default
RO 0