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Listing 20-5. Clear DMA Completion Interrupt
/* DMA0_IRQ_STATUS */
P2.L = lo(DMA0_IRQ_STATUS);
P2.H = hi(DMA0_IRQ_STATUS);
R2.L = W[P2];
BITSET(R2,0);
W[P2] = R2.L;
ssync;
Unique Information for the ADSP-BF50x
Processor
None.
ADSP-BF50x Blackfin Processor Hardware Reference
Parallel Peripheral Interface
20-37
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