Descriptor Queue Using Minimal Interrupts - Analog Devices ADSP-BF506F Hardware Reference Manual

If the counts are unequal, the software instead modifies the next-to-last
descriptor's
DMAx_CONFIG
now describes the newly queued descriptor. This operation does not dis-
rupt the DMA channel, provided the rest of the descriptor data structure
is initialized in advance. It is necessary, however, to synchronize the soft-
ware to the DMA to correctly determine whether the new or the old
value was read by the DMA channel.
DMAx_CONFIG
This synchronization operation should be performed in the interrupt
handler. First, upon interrupt, the handler should read the channel's
DMAx_IRQ_STATUS
has moved on to processing another descriptor, and the interrupt handler
may increment its count and exit. If the
ever, then the channel has paused, either because there are no more
descriptors to process, or because the last descriptor was queued too late
(the modification of the next-to-last descriptor's
occurred after that element was read into the DMA unit). In this case, the
interrupt handler should write the
last descriptor to the DMA channel's
completed descriptor count, and exit.
Again, this system can fail if the system's interrupt latencies are large
enough to cause any of the channel's DMA interrupts to be dropped. An
interrupt handler capable of safely synchronizing multiple descriptors'
interrupts would need to be complex, performing several MMR accesses to
ensure robust operation. In such a system environment, a minimal inter-
rupt synchronization method is preferred.

Descriptor Queue Using Minimal Interrupts

In this system, only one DMA interrupt event is possible in the queue at
any time. The DMA interrupt handler for this system can also be
extremely short. Here, the descriptor queue is organized into an "active"
and a "waiting" portion, where interrupts are enabled only on the last
descriptor in each portion.
ADSP-BF50x Blackfin Processor Hardware Reference
value so that its upper half (
register. If the
DMA_RUN
DMAx_CONFIG
Direct Memory Access
FLOW
status bit is set, then the channel
status bit is not set, how-
DMA_RUN
DMAx_CONFIG
value appropriate for the
register, increment the
DMAx_CONFIG
and )
NDSIZE
element
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