Analog Devices ADSP-BF506F Hardware Reference Manual page 256

Functional Description
B
A
C
D
Figure 7-2. DMA Flow, From DMA Controller's Point of View (2 of 2)
7-20
TEST NDSIZE
READ NDSIZE ELEMENTS
OF DESCRIPTOR INTO
PARAMETER REGISTERS
VIA CURRENT
DESCRIPTOR POINTER
FLOW = 0 OR 1
CLEAR DFETCH IN
IRQ_STATUS
DMA TRANSFER
BEGINS AND
CONTINUES UNTIL
COUNTS EXPIRE
TEST SYNC, WNR
SYNC = 0 OR
MEMORY WRITE
TEST DI_EN
DI_EN = 0
FLOW = 1
TEST FLOW
FLOW = 0
FLOW = 4, 6, 7
TEST SYNC, WNR
SYNC = 1 OR
MEMORY WRITE
DMA STOPPED.
CLEAR DMA_RUN IN
IRQ_STATUS.
ADSP-BF50x Blackfin Processor Hardware Reference
NDSIZE = 0 OR
NDSIZE > MAX_SIZE*
NDSIZE > 0 AND
NDSIZE <= MAX_SIZE*
SYNC = 1 &
MEMORY READ
DI_EN = 1
SYNC = 0 &
MEMORY READ
MEMORY WRITE (DESTINATION)
*MAX SIZE DEPENDS ON FLOW
IF FLOW = 4, MAX_SIZE = 7
IF FLOW = 6, MAX_SIZE = 8
IF FLOW = 7, MAX_SIZE = 9
DMA
ABORT
OCCURS
TRANSFER
DATA FROM
FIFO TO
PERIPHERAL
UNTIL EMPTY
SET DMA_DONE
IN IRQ_STATUS
TRANSFER
DATA FROM
FIFO TO
PERIPHERAL
UNTIL EMPTY