Mailbox Interrupts; Global Can Status Interrupt - Analog Devices ADSP-BF506F Hardware Reference Manual

Mailbox Interrupts

Each of the 32 mailboxes in the CAN module may generate a receive or
transmit interrupt, depending on the mailbox configuration. To enable a
mailbox to generate an interrupt, set the corresponding
.
CAN_MBIMx
If a mailbox is configured as a receive mailbox, the corresponding receive
interrupt flag is set (
stored in mailbox n (
handling feature is used, the receive interrupt flag is set after the requested
data frame is stored in the mailbox. If any
, the
CAN_MBRIFx
clear the
MBRIRQ
cleared by software by writing a 1 to those set bit locations in
If a mailbox is configured as a transmit mailbox, the corresponding trans-
mit interrupt flag is set (
mailbox n is sent correctly (
state even after the corresponding mailbox n is disabled (
automatic remote frame handling feature is used, the transmit interrupt
flag is set after the requested data frame is sent from the mailbox. If any
bits are set in
MBTIFn
. In order to clear the
CAN_INTR
bits must be cleared by software by writing a 1 to those set bit loca-
MBTIFn
tions in
CAN_MBTIFx

Global CAN Status Interrupt

The global CAN status interrupt logic is implemented with three regis-
ters—the global CAN interrupt mask register (
interrupt source can be enabled or disabled separately; the global CAN
interrupt status register (
ister ( ). The interrupt mask bits only affect the content of the
CAN_GIF
global CAN interrupt flag register (
corresponding flag bit is not set when the event occurs. The interrupt
ADSP-BF50x Blackfin Processor Hardware Reference
= in
MBRIFn 1 CAN_MBRIFx
= in
RMPn 1 CAN_RMPx
interrupt output is raised in
MBRIRQ
interrupt request, all of the set
=
MBTIFn 1
=
TAn 1
, the
CAN_MBTIFx
MBTIRQ
.
); and the global CAN interrupt flag reg-
CAN_GIS
) after a received message is
). If the automatic remote frame
bits are set in
MBRIFn
CAN_INTR
MBRIFn
in ) after the message in
CAN_MBTIFx
in ). The
CAN_TAx
interrupt output is raised in
MBTIRQ
interrupt request, all of the set
CAN_GIM
). If the mask bit is not set, the
CAN_GIF
CAN Module
bit in
MBIMn
. In order to
bits must be
CAN_MBRIFx
bits maintain
TAn
= 0). If the
MCn
), where each
17-23
.