System Interrupt Controller Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

System Interrupt Controller Registers

"INTERRUPT
A"
PERIPHERAL
INTERRUPT
REQUESTS
SYSTEM SYSTEM
WAKEUP STATUS
(SIC_IWR) (SIC_ISR)
TO DYNAMIC POWER
MANAGEMENT
CONTROLLER
SYSTEM INTERRUPT CONTROLLER
NOTE: NAMES IN PARENTHESES ARE MEMORY-MAPPED REGISTERS.
Figure 4-1. Interrupt Processing Block Diagram
System Interrupt Controller Registers
The SIC registers are described in the following sections.
These registers can be read from or written to at any time in supervisor
mode. It is advisable, however, to configure them in the reset interrupt
service routine before enabling interrupts. To prevent spurious or lost
interrupt activity, these registers should be written to only when all
peripheral interrupts are disabled.
4-10
SYSTEM ASSIGN
INTERRUPT SYSTEM
MASK PRIORITY
(SIC_IMASK) (SIC_IAR)
ADSP-BF50x Blackfin Processor Hardware Reference
EMU
RESET
NMI
EVX
IVTMR
IVHW
CORE
CORE
INTERRUPT
STATUS
MASK
(ILAT)
(IMASK)
CORE EVENT CONTROLLER
CORE
EVENT
VECTOR
TABLE
(EVT[15:0])
CORE
PENDING
(IPEND)