Uart Receive Operation - Analog Devices ADSP-BF506F Hardware Reference Manual

Description of Operation
bit goes high again and indicates that all pending transmit operation
TEMT
has finished. At that time it is safe to disable the
off-chip line drivers. An interrupt can be generated by that time either
through the status interrupt channel when the

UART Receive Operation

The receive operation uses the same data format as the transmit configura-
tion, except that one valid stop bit is always sufficient, that is, the
has no impact to the receiver.
The UART receiver is sensing the falling edges of the RX input. When an
edge is detected, the receiver starts sampling the RX input according to
the bit rate and the
midpoint. If sampled low, a valid start condition is assumed. Otherwise,
the detected falling edge is discarded.
After detection of the start bit, the received word is shifted into the inter-
nal shift register (
After the corresponding stop bit is received, the content of the
is transferred through the 4-deep receive FIFO to the
shown in Figure
are updated in the
also error conditions, if required.
The receive FIFOs and the
receive buffer. If the stop bit of the 6
reads the
UARTx_RBR
case protects data in the
ten by further data until the
register, however, is immediately destroyed as soon as the overrun
RSR
occurs.
15-8
bit settings. The start bit is sampled close to its
EDBO
at a bit rate characterized by the following formula:
RSR)
= ---------------------------------------------------- -
BIT RATE

16
15-13. Finally, the data ready (
register, to signal data reception, parity, and
UARTx_LSR
UARTx_RBR
register, an overrun error is reported. The overrun
UARTx_RBR
bit is cleared by software. The data in the
OE
ADSP-BF50x Blackfin Processor Hardware Reference
UCEN
bit is set.
ETFI
SCLK


–
1 EDB0
Divisor
) bit and the status flags
DR
registers can be seen as a five-stage
th
word is received before software
and receive FIFO from being overwrit-
bit or to three-state
bit
STB
register
RSR
register,
UARTx_RBR