L1 Data Cache; Boot Rom; External Memory - Analog Devices ADSP-BF506F Hardware Reference Manual

L1 Data Cache

L1 Data Cache
When data cache is enabled (controlled by bits
DMEM_CONTROL
cache.

Boot ROM

There are 4K bytes of memory space occupied by the boot ROM, starting
from address 0xEF00 0000. This 16-bit boot ROM is not part of the L1
memory module. Read accesses take one
required. The read-only memory can be read by the core as well as by
DMA. It can be cached and protected by CPLB blocks like external mem-
ory. The boot ROM not only contains boot-strap loader code, it also
provides some subfunctions that are user-callable at runtime. For more
information, see
and Booting.

External Memory

External memory (shown in
port. This 16-bit interface provides a glue-less connection to the internal
flash memory (on ADSP-BF504F and ADSP-BF506F devices) and boot
ROM. Internal flash memory ships from the factory in an erased state
except for block 0 of the parameter bank.

Block 0 of the flash memory parameter bank ships from the factory
in an unknown state. An erase operation should be performed prior
to programming this block.
2-4
register), 16K byte of data bank A can be set to serve as
"System Reset and Booting" in Chapter 24, System Reset
Figure
ADSP-BF50x Blackfin Processor Hardware Reference
DMC[1:0]
cycle and no wait states are
SCLK
2-1) is accessed via the EBIU memory
in the