Ppi Status Register (Ppi_Status) - Analog Devices ADSP-BF506F Hardware Reference Manual

The
XFR_TYPE[1:0]
tion. Refer to Table 20-1 on page 20-4
interacts with other bits in
mode.
The bit, when set, enables the PPI for operation.
PORT_EN

When configured as an input port, the PPI does not start data
transfer after being enabled until the appropriate synchronization
signals are received. If configured as an output port, transfer
(including the appropriate synchronization signals) begins as soon
as the frame syncs (timer units) are enabled, so all frame syncs must
be configured before this happens. Refer to
tion in GP Modes" on page 20-19

PPI Status Register (PPI_STATUS)

The
PPI_STATUS
vide information about the current operating state of the PPI.
The bit is a sticky bit that denotes whether or not an error was
ERR_DET
detected in the ITU-R 656 control word preamble. The bit is valid only in
ITU-R 656 modes. If
If = 0, no error was detected in the preamble.
ERR_DET
The
ERR_NCOR
= 0 and
ERR_NCOR
been corrected. If
not corrected. This situation generates a PPI error interrupt, unless this
condition is masked off in the
ADSP-BF50x Blackfin Processor Hardware Reference
field configures the PPI for various modes of opera-
PPI_CONTROL
register, shown in
= 1, an error was detected in the preamble.
ERR_DET
bit is sticky and is relevant only in ITU-R 656 modes. If
= 1, all preamble errors that have occurred have
ERR_DET
= 1, an error in the preamble was detected but
ERR_NCOR
SIC_IMASK
Parallel Peripheral Interface
to see how
XFR_TYPE[1:0]
to determine the PPI operating
"Frame Synchroniza-
for more information.
Figure 20-14, contains bits that pro-
register.
20-29