Analog Devices ADSP-BF506F Hardware Reference Manual page 119

6. masks off or enables events of different core priorities. If the
IMASK
event corresponding to interrupt A is not masked, the process
IVGx
proceeds to Step 7.
7. The event vector table (EVT) is accessed to look up the appropriate
vector for interrupt A's interrupt service routine (ISR).
8. When the event vector for interrupt A has entered the core pipe-
line, the appropriate
bit. Thus,
ILAT
being presently serviced.
9. When the interrupt service routine (ISR) for interrupt A has been
executed, the RTI instruction clears the appropriate
However, the relevant
rupt service routine clears the mechanism that generated interrupt
A, or if the process of servicing the interrupt clears this bit.
It should be noted that emulation, reset, NMI, and exception events, as
well as hardware error (
enter the interrupt processing chain at the
by the system-level interrupt registers (
).
SIC_IAR
If multiple interrupt sources share a single core interrupt, then the inter-
rupt service routine (ISR) must identify the peripheral that generated the
interrupt. The ISR may then need to interrogate the peripheral to deter-
mine the appropriate action to take.
ADSP-BF50x Blackfin Processor Hardware Reference
bit is set, which clears the respective
IPEND
tracks all pending interrupts, as well as those
IPEND
bit is not cleared unless the inter-
SIC_ISR
) and core timer (
IVHW
SIC_IWR
System Interrupts
IPEND
) interrupt requests,
IVTMR
level and are not affected
ILAT
, ,
SIC_ISR SIC_IMASK
bit.
,
4-9