Latency Bits (Cr13-Cr11); Wait Polarity Bit (Cr10) - Analog Devices ADSP-BF506F Hardware Reference Manual

are asynchronous; when the read select bit is set to '0', read operations are
synchronous. Synchronous burst read is supported in both parameter and
main blocks and can be performed across banks.
On reset or power-up the read select bit is set to '1' for asynchronous
access.
X Latency Bits (CR13-CR11)
The X latency bits are used during synchronous read operations to set the
number of clock cycles between the address being latched and the first
data becoming available. For correct operation the X latency bits can only
assume the values in
Table 6-8 shows how to set the X latency parameter, taking into account
the frequency used to read the internal flash memory in synchronous
mode.
Table 6-8. Latency Settings
f max
K
30 MHz
40 MHz
50 MHz

Wait Polarity Bit (CR10)

In synchronous burst mode, the
data are valid or a wait state must be inserted. The wait polarity bit is used
to set the polarity of the
'0' the signal is active low. When the wait polarity bit is set to '1' the
WAIT
signal is active high.
WAIT
ADSP-BF50x Blackfin Processor Hardware Reference
Table 6-9 on page
t min
K
33 ns
25 ns
19 ns
signal indicates whether the output
WAIT
signal. When the wait polarity bit is set to
WAIT
Internal Flash Memory
6-28.
X latency min
2
3
4
6-25