Clock Stretching During Fifo Overflow - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description

Clock Stretching During FIFO Overflow

During a master mode receive, an interrupt is generated at the instant the
receive FIFO becomes full. It is during the acknowledge phase of this
received byte that clock stretching begins. No attempt is made to initiate
the reception of an additional byte. Stretching of the clock continues until
the data bytes previously received are read from the receive FIFO buffer
(
TWI_RCV_DATA8
the clock and continue the reception of data. This behavior continues
until the reception is complete (
is concluded (
MCOMP
Table 16-6.
S ADDRESS
RCVSTAT[1:0]
ACKNOWLEDGE "STRETCH" BEGINS SOON AFTER SCL FALL.
Figure 16-10. Clock Stretching During FIFO Overflow
16-20
, ). No other action is required to release
TWI_RCV_DATA16
DCNT
) as shown in Figure 16-10
R/W
ACK DATA ACK
00
ACKNOWLEDGE WITH STRETCH
SCL
ADSP-BF50x Blackfin Processor Hardware Reference
= 0x00) at which time the reception
and described in
ACK WITH
DATA DATA
STRETCH
01 11
TWI_RCV_DATA IS READ AT THIS TIME AND
CLOCK STRETCHING IS RELEASED.
00