Analog Devices ADSP-BF506F Hardware Reference Manual page 106

Interface Overview
The DCB has priority over the core processor on arbitration into L1 con-
figured as data SRAM, whereas the core processor has priority over the
DCB on arbitration into L1 instruction SRAM. For external memory
(flash memory on ADSP-BF50xF processors), the core (by default) has
priority over the DEB for accesses to the EPB. The processor has a pro-
grammable priority arbitration policy on the DAB.
default arbitration priority. In addition, by setting the
register, all DEB transactions to the EPB have priority over
EBIU_AMGCTL
core accesses to external memory. Use of this bit is application-dependent.
For example, if you are polling a peripheral mapped to asynchronous
memory with long access times, by default the core will "win" over DMA
requests. By setting the
requests were serviced.
Table 3-1. DAB, DCB, and DEB Arbitration Priority
DAB, DCB, DEB Master
PPI receive or transmit
RSI receive or transmit
SPORT0 receive
SPORT0 transmit
SPORT1 receive
SPORT1 transmit
SPI0 receive or transmit
SPI1 receive or transmit
UART0 receive
UART0 transmit
UART1 receive
UART1 transmit
Mem DMA D0 has no peripheral mapping
Mem DMA S0 has no peripheral mapping
3-8
bit, the core would be held off until DMA
CDPRIO
Default Arbitration Priority
0 - highest
1
2
3
4
5
6
7
8
9
10
11
None
None
ADSP-BF50x Blackfin Processor Hardware Reference
Table 3-1 shows the
bit in the
CDPRIO