Analog Devices ADSP-BF506F Hardware Reference Manual page 314

DMA Registers
DMA Current Inner Loop Count Registers (DMAx_CURR_X_COUNT/
MDMA_yy_CURR_X_COUNT)
R/W prior to enabling channel; RO after enabling channel
15 14 13 12 11 10
X X X X X
Figure 7-11. DMA Current Inner Loop Count Registers
DMA Inner Loop Address Increment Registers
(DMAx_X_MODIFY/MDMA_yy_X_MODIFY)
The
DMAx_X_MODIFY
two's-complement byte-address increment. In 1-D DMA, this increment
is the stride that is applied after transferring each element.

DMAx_X_MODIFY
size.
In 2-D DMA, this increment is applied after transferring each element in
the inner loop, up to but not including the last element in each inner
loop. After the last element in each inner loop, the
is applied instead, except on the very last transfer of each work unit. The
DMAx_X_MODIFY
The
DMAx_X_MODIFY
repeatedly to or from the same address. This is useful, for example, in
transferring data between a data register and an external memory-mapped
peripheral.
7-78
9 8 7 6 5 4
X X X X X X X
register, shown in
is specified in bytes, regardless of the DMA transfer
register is always applied to the last transfer of a work unit.
field may be set to 0. In this case, DMA is performed
ADSP-BF50x Blackfin Processor Hardware Reference
3 2 1 0
Reset = Undefined
X X X X
CURR_X_COUNT[15:0]
(Current Inner Loop
Count)
Loaded by X_COUNT
at the beginning of each
DMA session (1-D DMA),
or at the beginning of
each row (2-D DMA)
Figure 7-12, contains a signed,
DMAx_Y_MODIFY
register