Spi Control (Spi_Ctl) Register - Analog Devices ADSP-BF506F Hardware Reference Manual

SPI Registers

SPI Control (SPI_CTL) Register

The register is used to configure and enable the SPI system. This
SPI_CTL
register is used to enable the SPI interface, select the device as a master or
slave, and determine the data transfer format and word size.
The term "word" refers to a single data transfer of either 8 bits or 16 bits,
depending on the word length (
bits which can also be modified by the hardware:
The field is used to specify the action that initiates transfers to/from
TIMOD
the receive/transmit buffers. When set to
begun when the receive buffer is read. Data from the first read will need to
be discarded since the read is needed to initiate the first SPI port transac-
tion. When set to
buffer is written. A value of
transaction is initiated by enabling the SPI for DMA receive mode. Subse-
quent individual transactions are initiated by a DMA read of the
register. A value of 11 selects DMA transmit mode and the transaction is
initiated by a DMA write of the
The bit is used to enable the
PSSE
When not used,
function.
The bit enables the
EMISO
environment where the master wishes to transmit to various slaves at one
time (broadcast). Only one slave is allowed to transmit data back to the
master. Except for the slave from whom the master wishes to receive, all
other slaves should have this bit cleared.
The and
SPE MSTR
the register is set. See
SPI_STAT
page 18-41.
18-36
SIZE
, the transaction is initiated when the transmit
b#01
selects DMA receive mode and the first
b#10
SPI_TDBR
SPISS
can be disabled, freeing up a pin for an alternate
SPISS
pin as an output. This is needed in an
MISO
bits can be modified by hardware when the
"Mode Fault Error (MODF)" on
ADSP-BF50x Blackfin Processor Hardware Reference
) bit in . There are two special
SPI_CTL
and
SPE
, a SPI port transaction is
b#00
register.
input for an external master.
.
MSTR
SPI_RDBR
bit of
MODF