Analog Devices ADSP-BF506F Hardware Reference Manual page 340

Unique Information for the ADSP-BF50x Processor
CCLK SCLK
DMA TRAFFIC CONTROL
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
FIFO
16 16
DCB DEB
Figure 7-28. ADSP-BF50x DMA Controller Block Diagram
7-104
MDMA 0 SOURCE CONTROL
MDMA 0 DESTINATION CONTROL
MDMA 1 SOURCE CONTROL
MDMA 1 DESTINATION CONTROL
PMAP
PMAP
PMAP
PMAP
PMAP
PMAP
PMAP
PMAP
PMAP
PMAP
PMAP
PMAP
16 12 3 x 12
DAB DGT DRQ
ADSP-BF50x Blackfin Processor Hardware Reference
DMA 11 CONTROL
DMA 10 CONTROL
DMA 9 CONTROL
DMA 8 CONTROL
DMA 7 CONTROL
DMA 6 CONTROL
DMA 5 CONTROL
DMA 4 CONTROL
DMA 3 CONTROL
DMA 2 CONTROL
DMA 1 CONTROL
DMA 0 CONTROL
IRQ 1
IRQ 42
IRQ 43
IRQ 25
IRQ 24
IRQ 23
IRQ 22
IRQ 21
IRQ 20
IRQ 19
IRQ 18
IRQ 17
IRQ 16
IRQ 15
IRQ 14
16
PAB