Ceata_Int_Dis State; Ceata_Int_Wait State - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description
CMD_CRC_FAIL
tions to the IDLE state.
Some CE-ATA commands require additional functionality upon reaching
this state. This additional functionality requires sending a command
completion signal back to the host upon completion of a specific task.
For commands that require this functionality, the
CEATA_CCS_EN
enabling the command path state machine. After receiving the response,
the state machine then enters the CEATA_INT_WAIT state.

CEATA_INT_WAIT State

Upon entering this state, the RSI waits for the CE-ATA device to issue the
command completion signal. This is indicated by the device sending a "0"
on the
RSI_CMD
nal, the
CMD_ACT
register is set. Alternatively, the command completion signal of
RSI_ESTAT
the CE-ATA device can be disabled by the RSI. This action is performed
by setting the
CEATA_TX_CCSD
which point the state machine enters the CEATA_INT_DIS state. The
CEATA_TX_CCSD
machine. This will result in the CCSD sequence being issued after the
response is received rather than having to wait for the response then set-
ting this
CEATA_TX_CCSD

CEATA_INT_DIS State

Upon entering this state, the RSI issues the command completion signal
disable sequence on the
IDLE state and clearing the
signal disable sequence issued is the binary sequence "00001".
21-22
flag being set. At this point the state machine then transi-
bits of the
RSI_DATA_CONTROL
signal. Upon detection of the command completion sig-
flag is cleared and the
bit of the
bit can be set prior to enabling the command path state
.
RSI_CMD
CMD_ACT
ADSP-BF50x Blackfin Processor Hardware Reference
CEATA_EN
register should be set prior to
CEATA_INT_DET
RSI_CEATA_CONTROL
signal before then transitioning to the
flag. The command completion
and
flag of the
register, at