Dma Controller Overview; External Interfaces; Internal Interfaces - Analog Devices ADSP-BF506F Hardware Reference Manual

DMA Controller Overview

• 2-D DMA, using an array of 1-word descriptors, specifying only
the base DMA address within a common data page
• 2-D DMA, using a linked list of 9-word descriptors specifying
everything
DMA Controller Overview
A block diagram of the DMA controller can be found in the
Information for the ADSP-BF50x Processor" on page

External Interfaces

The DMA does not connect external memories and devices directly.
Rather, data is passed through the EBIU port. Any kind of device that is
supported by the EBIU can also be accessed by peripheral DMA or mem-
ory DMA operation. This is typically flash memory, SRAM, SDRAM,
FIFOs, or memory-mapped peripheral devices.
For products with handshaking MDMA (HMDMA), the operation is sup-
ported by two MDMA request input pins,
pin controls transfer timing on the
pin controls the destination channel of
FIFO devices, ADC or DAC converters, or other streaming or block-pro-
cessing devices can use the MDMA channels to exchange their data or
data buffers with the Blackfin processor memory.

Internal Interfaces

Figure 3-1 on page 3-3
controller to interconnect L1 memory, the on-chip peripherals, and the
EBIU port.
7-4
MDMA0
shows the dedicated DMA buses used by the DMA
ADSP-BF50x Blackfin Processor Hardware Reference
7-103.
and
DMAR0 DMAR1
destination channel. The
. With these pins, external
MDMA1
"Unique
. The
DMAR0
DMAR1