Timer Overview; External Interfaces - Analog Devices ADSP-BF506F Hardware Reference Manual

Timer Overview

inside the Blackfin core and runs at the core clock (
features include:
• 32-bit timer with 8-bit prescaler
• Operates at core clock (
• Dedicated high-priority interrupt channel
• Single-shot or continuous operation
Timer Overview
Figure 11-1 provides a block diagram of the core timer.
CCLK
Figure 11-1. Core Timer Block Diagram

External Interfaces

The core timer does not directly interact with any pins of the chip.
11-2
) rate
CCLK
CORE REGISTER ACCESS BUS (RAB)
TSCALE
TCNTL
TIMER ENABLE
AND PRESCALE DEC
LOGIC
ADSP-BF50x Blackfin Processor Hardware Reference
CCLK
32
TPERIOD
COUNT REGISTER
LOAD LOGIC
ZERO
TCOUNT
) rate. Core timer
TIMER
INTERRUPT