Analog Devices ADSP-BF506F Hardware Reference Manual page 279

When the traffic on all DMA channels is taken in the aggregate:
• Transfers between the peripherals and the DMA unit have a maxi-
mum rate of one 16-bit transfer per system clock.
• Transfers between the DMA unit and internal memory (L1) have a
maximum rate of one 16-bit transfer per system clock.
• Transfers between the DMA unit and external memory have a
maximum rate of one 16-bit transfer per system clock.
Some considerations which limit the actual performance include:
• Accesses to internal or external memory which conflict with core
accesses to the same memory. This can cause delays, for example
when both the core and the DMA access the same L1 bank, when
SDRAM pages need to be opened/closed, or when cache lines are
filled.
• Direction changes from
cycle delay.
SCLK
• Direction changes on the DCB bus (for example, write followed by
read) to the same bank of internal memory can impose delays.
• Direction changes (for example, read followed by write) on the
DEB bus to external memory can each impose a several-cycle delay.
• MMR accesses to DMA registers other than
DMAx_IRQ_STATUS
for one cycle per 16-bit word transferred. In contrast, MMR
accesses to the control/status registers do not cause stalls or wait
states.
• Reads from DMA registers other than control/status registers use
one PAB bus wait state, delaying the core for several core clocks.
ADSP-BF50x Blackfin Processor Hardware Reference
to on the DAB bus impose a one
RX TX
, or
DMAx_PERIPHERAL_MAP
Direct Memory Access
DMAx_CONFIG
stall all DMA activity
,
7-43