Analog Devices ADSP-BF506F Hardware Reference Manual page 965

signals. In other words, the
being processed by the PPI.
The bit is sticky and indicates, when set, that the PPI FIFO has over-
OVR
flowed and can accept no more data. A FIFO overflow error generates a
PPI error interrupt, unless this condition is masked off in the
register.

The PPI FIFO is 16 bits wide and has 16 entries.
The bit is sticky and indicates, when set, that the PPI FIFO has
UNDR
underrun and is data-starved. A FIFO underrun error generates a PPI
error interrupt, unless this condition is masked off in the
register.
The
LT_ERR_OVR
that a line track error has occurred. These bits are valid for RX modes with
recurring frame syncs only. If one of these bits is set, the programmed
number of samples in
of samples counted between assertions of
modes) or start of active video (SAV) codes (for ITU-R 656 modes). If the
PPI error interrupt is enabled in the
request is generated when one of these bits is set.
The
LT_ERR_OVR
occurred, where the value in
code was received. This flag does not apply for non ITU-R 656 modes; in
this case, once the value in
counting until receiving the next
The
LT_ERR_UNDR
occurred, where a new SAV code or
value in
PPI_COUNT
ADSP-BF50x Blackfin Processor Hardware Reference
bit always reflects the current video field
FLD
and bits are sticky and indicate, when set,
LT_ERR_UNDR
did not match up with the actual number
PPI_COUNT
flag signifies that a horizontal tracking overflow has
PPI_COUNT
PPI_COUNT
PPI_FS1
flag signifies that a horizontal tracking underflow has
was reached.
Parallel Peripheral Interface
(for general-purpose
PPI_FS1
register, an interrupt
SIC_IMASK
was reached before a new SAV
is reached, the PPI simply stops
frame sync.
assertion occurred before the
PPI_FS1
SIC_IMASK
SIC_IMASK
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