Ppi Lines Per Frame Register (Ppi_Frame) - Analog Devices ADSP-BF506F Hardware Reference Manual


Take care to ensure that the number of samples programmed into
PPI_COUNT
ing the "horizontal" interval specified by
PPI Transfer Count Register (PPI_COUNT)
15 14 13 12 11 10
0 0 0 0
Figure 20-16. PPI Transfer Count Register

PPI Lines Per Frame Register (PPI_FRAME)

The
PPI_FRAME
modes with two or three frame syncs. For ITU-R 656 modes, this register
holds the number of lines expected per frame of data, where a frame is
defined as field 1 and field 2 combined, designated by the
the ITU-R stream. Here, a line is defined as a complete ITU-R 656
SAV-EAV cycle.
For non ITU-R 656 modes with external frame syncs, a frame is defined as
the data bounded between
. A line is defined as a complete
PPI_FS3
is used only to determine the original "frame start" each time the
PPI_FS3
PPI is enabled. It is ignored on every subsequent field and frame, and its
state (high or low) is not important except during the original frame start.
If the start of a new frame (or field, for ITU-R 656 mode) is detected
before the number of lines specified by
frame track error results, and the
ADSP-BF50x Blackfin Processor Hardware Reference
is in keeping with the number of samples expected dur-
9 8 7 6 5 4
0 0 0 0 0 0 0 0
register, shown in
PPI_FS2
FT_ERR
Parallel Peripheral Interface
PPI_FS1
3 2 1 0
Reset = 0x0000
0 0 0 0
PPI_COUNT[15:0]
In RX modes, holds one less
than the number of samples to
read in to the PPI per line. In
TX modes, holds one less
than the number of samples to
write out through the PPI per
line.
Figure 20-17, is used in all TX and RX
assertions, regardless of the state of
cycle. In these modes,
PPI_FS1
have been transferred, a
PPI_FRAME
bit in
PPI_STATUS
.
indicator in
F
is set.
20-33