Serial Peripheral Interface (Spi) Ports; Timers - Analog Devices ADSP-BF506F Hardware Reference Manual

Serial Peripheral Interface (SPI) Ports

Serial Peripheral Interface (SPI) Ports
The processor has two SPI-compatible ports that enable the processor to
communicate with multiple SPI-compatible devices.
Each SPI interface uses three pins for transferring data: two data pins and
a clock pin. An SPI chip select input pin lets other SPI devices select the
processor, and several SPI chip select output pins let the processor select
other SPI devices. The SPI select pins are reconfigured general-purpose
I/O pins. Using these pins, the SPI port provides a full-duplex, synchro-
nous serial interface, which supports both master and slave modes and
multimaster environments.
Each SPI port's baud rate and clock phase/polarities are programmable,
and it has an integrated DMA controller, configurable to support either
transmit or receive data streams. The SPI's DMA controller can only ser-
vice unidirectional accesses at any given time.
During transfers, the SPI port simultaneously transmits and receives by
serially shifting data in and out of its two serial data lines. The serial clock
line synchronizes the shifting and sampling of data on the two serial data
lines.

Timers

There are nine general-purpose programmable timer units in the proces-
sor. Eight timers have an external pin that can be configured either as a
Pulse Width Modulator (PWM) or timer output, as an input to clock the
timer, or as a mechanism for measuring pulse widths of external events.
These timer units can be synchronized to an external clock input con-
nected to the
TMRCLK
The timer units can be used in conjunction with the UARTs to measure
the width of the pulses in the datastream to provide an autobaud detect
function for a serial channel.
1-18
/ pin or to the internal
PPI_CLK
ADSP-BF50x Blackfin Processor Hardware Reference
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SCLK