Dma Performance - Analog Devices ADSP-BF506F Hardware Reference Manual

interrupt status bits require a write-1-to-clear operation to cancel the
interrupt request.
The
block done
defined by the
HMDMAx_BCOUNT
this interrupt, the
zero, meaning that all requested MDMA transfers have been completed.
The overflow interrupt is generated when the HMDMA_ECOUNT regis-
ter overflows. Since it can count up to 32767, which is much more than
most peripheral devices can support, the Blackfin processor has another
threshold register called HMDMA_ECOVERFLOW. It resets to 0xFFFF
and should be written with any positive value by the user before enabling
the function by the OIE bit. Then, the overflow interrupt is issued when
the value of the HMDMA_ECOUNT register exceeds the threshold in
the HMDMA_ECOVERFLOW register.

DMA Performance

The DMA system is designed to provide maximum throughput per chan-
nel and maximum utilization of the internal buses, while accommodating
the inherent latencies of memory accesses.
The Blackfin architecture features several mechanisms to customize system
behavior for best performance. This includes DMA channel prioritization,
traffic control, and priority treatment of bursted transfers. Nevertheless,
the resulting performance of a DMA transfer often depends on applica-
tion-level circumstances. For best performance consider the following
system software architecture questions:
• What is the required DMA bandwidth?
• Which DMA transfers have real-time requirements and which do
not?
ADSP-BF50x Blackfin Processor Hardware Reference
interrupt signals that a complete MDMA block, as
register, has been transferred (when the
HMDMAx_BCINIT
register decrements to zero). While the
bit can gate it until the edge count also becomes
MBDI
Direct Memory Access
bit enables
BDIE
7-41