Analog Devices ADSP-BF506F Hardware Reference Manual page 598

Interface Overview
EIA-232, EIA-422, 4-wire EIA-485) or half duplex (for example, 2-wire
EIA-485, LIN) standards. Additionally, each UART features a pair of
(clear to send, input) and
UARTxCTS
nals for hardware flow control.
All UART signals are multiplexed and compete with other functions at
pin level. Table 15-1
are enabled in the port control.
Table 15-1. UART Signals
Signal
UART0 TX
UART0 RX
UART0 RTS
UART0 CTS
UART1 TX
UART1 RX
UART1 RTS
UART1 CTS
15-4
shows where the signal can be found and how they
Pin Port Control
PF1 PORTF_MUX[3:2] = b#01
(or PG13) PORTF_FER[1] = 1
(or PORTG_MUX[13:12] = b#00
PORTG_FER[13] = 1)
PF0 PORTF_MUX[1:0] = b#01
(or PG12) PORTF_FER[0] = 1
(or PORTG_MUX[13:12] = b#00
PORTG_FER[12] = 1)
PG14 PORTG_MUX[15:14] = b#00
PORTG_FER[14] = 1
PG15 PORTG_MUX[15:14] = b#00
PORTG_FER[15] = 1
PF6 PORTF_MUX[7:6] = b#00
(or PG3) PORTF_FER[6] = 1
(or PORTG_MUX[7:6] = b#10
PORTG_FER[3] = 1)
PF7 PORTF_MUX[7:6] = b#00
(or PG0) PORTF_FER[7] = 1
(or PORTG_MUX[1:0] = b#10
PORTG_FER[0] = 1)
PF8 PORTF_MUX[9:8] = b#00
PORTF_FER[8] = 1
PF9 PORTF_MUX[9:8] = b#00
PORTF_FER[9] = 1
ADSP-BF50x Blackfin Processor Hardware Reference
(request to send, output) sig-
UARTxRTS
Autobaud Timer
-
Timer 6 (TMR6)
(or Timer 2 (TACI2))
-
-
-
Timer 3 (TACI3)
(or Timer 4 (TACI4))
-
-