Analog Devices ADSP-BF506F Hardware Reference Manual page 1023

for a 4096 byte read transfer. The
set to 4. The
(a word size of 32-bits and direction set to memory write).
6. Write the number of bytes to be transferred to the
register. This will be 4096 for eight blocks of 512 bytes.
7. Write the appropriate timeout value for a read operation to the
RSI_DATA_TIMER
8. Write the source start address to the
supplied address must be aligned to a 512-byte boundary if mis-
aligned accesses are not enabled and the card is not a high-capacity
SD card or a sector-addressable MMC card.
9. Enable the data path state machine by writing to the
RSI_DATA_CONTROL
512-byte block.
be set to enable the data path state machine. Set the transfer direc-
tion from card to controller and allow the DMA controller access
to the receive FIFO. All other fields of the
ter should be zero.
10.Write the
ister, configuring the command path state machine to expect a
short response by setting
response type is R1.
11.Unlike core accesses, it is safe to poll on
within the
detected via the
enabled in step 5 will ensure any data sent to the receive FIFO
prior to the
ADSP-BF50x Blackfin Processor Hardware Reference
register should be set for DMA enable
DMAx_CONFIG
register.
register with
,
DATA_EN DATA_DIR
READ_MULTIPLE_BLOCK
CMD_RESP
register and clear the status bit once
RSI_STATUS
RSI_STATUSCL
flag being set is received correctly.
CMD_RESP_END
Removable Storage Interface
DMAx_X_MODIFY
RSI_ARGUMENT
set to 9 for a
DATA_BLK_LGTH
, and
DATA_DMA_EN
RSI_DATA_CONTROL
command to the
and clearing
CMD_L_RESP
CMD_RESP_END
register. The DMA controller,
register should be
RSI_DATA_LGTH
register. The
should also
regis-
reg-
RSI_COMMAND
. The
indication
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