Analog Devices ADSP-BF506F Hardware Reference Manual page 583

Table 14-4. PWM_CTRL Register
Bit Name
0 PWM_EN
Hardware modifiable bit.
1 PWM_SYNC_EN
2 PWM_DBL
3 PWM_EXTSYNC
4 PWM_SYNCSEL
5 PWM_POLARITY
6 PWM_SRMODE
7 PWMTRIPINT_EN
8 PWMSYNCINT_EN
9 PWMTRIP_DSBL
15:10 Reserved
ADSP-BF50x Blackfin Processor Hardware Reference
Function
PWM enable
0 = disabled
1 = enabled
reset by
PWM_TRIP
PWM sync enable
0 = disabled
1 = enabled
Double-update mode
0 = single-update mode
1 = double-update mode
External sync
0 = internal sync
1 = external sync
External sync select
0 = asynchronous
1 = synchronous
PWM output polarity
1 = active high
0 = active low
PWM SR Mode
0 = enabled
1 = disabled
Interrupt enable for trip
1 = enabled
0 = disabled
Interrupt enable for sync
1 = enabled
0 = disabled
Disable for trip input
1 = disabled
0 = enabled
PWM Controller
Type Default
RW 0
RW 0
RW 0
RW 0
RW 1
RW 1
RW 1
RW 0
RW 0
RW 0
0
14-39