Analog Devices ADSP-BF506F Hardware Reference Manual page 830

Programming Model
In transmit mode, as long as there is room in the SPI DMA FIFO
(the FIFO is not full), the SPI continues to request a DMA read
from memory. The DMA engine continues to read a word from
memory and write to the SPI DMA FIFO until the SPI DMA word
count register transitions from "1" to "0". The SPI continues trans-
mitting words until the SPI DMA FIFO is empty.
See Figure 18-9 on page 18-31
For receive DMA operations, if the DMA engine is unable to keep up with
the receive datastream, the receive buffer operates according to the state of
the bit in the
GM
device continues to receive new data from the
older data in the
the incoming data is discarded, and the
While performing receive DMA, the transmit buffer is assumed to be
empty (and
TXE
the pin. If
MOSI
register. The
SPI_TDBR
interrupt in this mode.
For transmit DMA operations, the master SPI initiates a word transfer
only when there is data in the DMA FIFO. If the DMA FIFO is empty,
the SPI waits for the DMA engine to write to the DMA FIFO before start-
ing the transfer. All aspects of SPI receive operation should be ignored
when configured in transmit DMA mode, including the data in the
register, and the status of the
SPI_RDBR
run conditions cannot generate an error interrupt in this mode. The
underrun condition cannot happen in this mode (master DMA
because the master SPI will not initiate a transfer if there is no data in the
DMA FIFO.
Writes to the
SPI_TDBR
tion should not occur because the DMA data will be overwritten. Writes
18-26
for additional information.
register. If
SPI_CTL
register. If
SPI_RDBR
is set). If = 1, the device repeatedly transmits zeros on
SZ
= 0, it repeatedly transmits the contents of the
SZ
underrun condition cannot generate an error
TXE
register during an active SPI transmit DMA opera-
ADSP-BF50x Blackfin Processor Hardware Reference
= 1 and the DMA FIFO is full, the
GM
pin, overwriting the
MISO
= 0, and the DMA FIFO is full,
GM
register is not updated.
SPI_RDBR
and bits. The
RXS RBSY
over-
RBSY
TXE
mode),
TX