Analog Devices ADSP-BF506F Hardware Reference Manual page 472

Timer Registers
Table 10-2. Control Bit and Register Usage Chart (Cont'd)
Bit / Register
Counter
TRUN
TOVF_ERR
IRQ
10-48
PWM_OUT Mode
RO: Counts up on
SCLK or PWM_CLK
Read: Timer slave
enable status
Write:
1 - Stop timer if dis-
abled
0 - No effect
Set at startup or roll-
over if period = 0 or 1
Set at rollover if width
>= Period
Set if counter wraps
Depends on
IRQ_ENA:
1 - Set when
TOVF_ERR set or
when counter equals
period and
PERIOD_CNT = 1 or
when counter equals
width and
PERIOD_CNT = 0
0 - Not set
ADSP-BF50x Blackfin Processor Hardware Reference
WDTH_CAP Mode
RO: Counts up on
SCLK
Read: Timer slave
enable status
Write:
1 - No effect
0 - No effect
Set if counter wraps
Depends on
IRQ_ENA:
1 - Set when
TOVF_ERR set or
when counter captures
period and
PERIOD_CNT = 1 or
when counter captures
width and
PERIOD_CNT = 0
0 - Not set
EXT_CLK Mode
RO: Counts up on
TMR pin event
Read: Timer slave
enable status
Write:
1 - No effect
0 - No effect
Set if counter wraps or
set at startup or roll-
over if period = 0
Depends on
IRQ_ENA:
1 - Set when counter
equals period or
TOVF_ERR set
0 - Not set