Analog Devices ADSP-BF506F Hardware Reference Manual page 634

UART Registers
UART Interrupt Enable Set Registers (UARTx_IER_SET)
15 14 13 12 11 10
For memory-
0 0
mapped
addresses,
see Table 15-11.
ERFCI (Enable Receive FIFO Count Interrupt)
0 - No interrupt
1 - Generate status interrupt if RFCS
bit in UARTx_MSR is set
ETFI (Enable Transmission Finished Interrupt)
0 - No interrupt
1 - Generate status interrupt if
TFI bit in UARTx_LSR is set
Unused
EDSSI (Enable Modem Status Interrupt)
0 - No interrupt
1 - Generate status interrupt
if SCTS bit in UARTx_MSR is set
Figure 15-14. UART Interrupt Enable Set Registers
Table 15-11. UART Interrupt Enable Set Register Memory-Mapped
Addresses
Register Name
UART0_IER_SET
UART1_IER_SET
15-40
9 8 7 6
0 0 0 0 0 0 0 0
Memory-Mapped Address
0xFFC0 0420
0xFFC0 2020
ADSP-BF50x Blackfin Processor Hardware Reference
5 4 3 2 1 0
Reset = 0x0000
0 0 0 0 0 0
ERBFI (Enable Receive Buf-
fer Full Interrupt)
0 - No interrupt
1 - Generate RX interrupt if
ETBEI (Enable Transmit
Buffer Empty Interrupt)
0 - No interrupt
1 - Generate TX interrupt if
THRE bit in UARTx_LSR is
ELSI (Enable RX Status
Interrupt)
0 - No interrupt
1 - Generate status interrupt
if any of UARTx_LSR[4:1] is
set
DR bit in UARTx_LSR is
set
set