Active Low Versus Active High Frame Syncs - Analog Devices ADSP-BF506F Hardware Reference Manual

When = 1 or
ITFS
ated internally by the SPORT, and the
The frequency of the frame sync signal is determined by the value of the
frame sync divisor in the
When = 0 or
ITFS
accepted as an input on the
in the
SPORT_TFSDIV
All of the frame sync options are available whether the signal is generated
internally or externally.

Active Low Versus Active High Frame Syncs

Frame sync signals may be either active high or active low (in other words,
inverted). The
ters determine frame sync logic levels:
• When
LTFS
active high.
• When
LTFS
active low.
Active high frame syncs are the default. The
ized to 0 after a processor reset.
Sampling Edge for Data and Frame Syncs
Data and frame syncs can be sampled on either the rising or falling edges
of the SPORT clock signals. The TCKFE and RCKFE bits of the
SPORT_TCR1 and SPORT_RCR1 registers select the driving and sam-
pling edges of the serial data and frame syncs.
For the SPORT transmitter, setting
selects the falling edge of
frame syncs and selects the rising edge of
ADSP-BF50x Blackfin Processor Hardware Reference
= 1, the corresponding frame sync signal is gener-
IRFS
SPORT_TFSDIV
= 0, the corresponding frame sync signal is
IRFS
pin or
TFS
/
SPORT_RFSDIV
and bits of the
LTFS LRFS
= 0 or = 0, the corresponding frame sync signal is
LRFS
= 1 or = 1, the corresponding frame sync signal is
LRFS
to drive data and internally generated
TSCLK
pin or
TFS RFS
or
SPORT_RFSDIV
pin, and the frame sync divisors
RFS
registers are ignored.
and
SPORT_TCR1
and
LTFS
= 1 in the
TCKFE SPORT_TCR1
to sample externally
TSCLK
SPORT Controller
pin is an output.
register.
regis-
SPORT_RCR1
bits are initial-
LRFS
register
19-33