Description Of Operation; Spi Transfer Protocols - Analog Devices ADSP-BF506F Hardware Reference Manual

Description of Operation


When using DMA for SPI transmit, the
fies that the DMA FIFO is empty. However, at this point there
may still be data in the SPI DMA FIFO waiting to be transmitted.
Therefore, software needs to poll
it goes low for two successive reads, at which point the SPI DMA
FIFO will be empty. When the
last word has been transferred.
The four-word FIFO is cleared when the SPI port is disabled.
Description of Operation
The following sections describe the operation of the SPI.

SPI Transfer Protocols

The SPI protocol supports four different combinations of serial clock
phase and polarity (SPI modes 0, 1, 2, 3). These combinations are selected
using the
CPOL
Figure 18-6 on page 18-14
the two basic transfer formats as defined by the
are shown for
SCK
grams may be interpreted as master or slave timing diagrams since the
, and
MISO MOSI
slave. The
MISO
and the signal is the output from the master (master transmission).
MOSI
The signal is generated by the master, and the
SCK
device select input to the slave from the master. The diagrams represent an
8-bit transfer (
( = 0). Any combination of the
LSBF
allowed. For example, a 16-bit transfer with the least significant bit (LSB)
first is another possible configuration.
18-12
and bits in
CPHA SPI_CTL
and Figure 18-7 on page 18-14
—one for
CPOL
pins are directly connected between the master and the
signal is the output from the slave (slave transmission),
= 0) with the most significant bit (MSB) first
SIZE
ADSP-BF50x Blackfin Processor Hardware Reference
DMA_DONE
in the
TXS SPI_STAT
bit subsequently gets set, the
SPIF
as shown in
CPHA
= 0 and the other for
SPISS
and bits of
SIZE LSBF
interrupt signi-
register until
Figure 18-5.
demonstrate
bit. Two waveforms
= 1. The dia-
CPOL
SCK
signal is the slave
is
SPI_CTL
,