Analog Devices ADSP-BF506F Hardware Reference Manual page 399

General-Purpose Ports
Then, an interrupt request can be generated according to the state of the
pin (either high or low), an edge transition (low to high or high to low), or
on both edge transitions (low to high and high to low). Input sensitivity is
defined on a per-bit basis by the GPIO polarity registers ( ,
PORTFIO_POLAR
, and ), and the GPIO interrupt sensitivity
PORTGIO_POLAR PORTHIO_POLAR
registers ( , , and ). If configured
PORTFIO_EDGE PORTGIO_EDGE PORTHIO_EDGE
for edge sensitivity, the GPIO set on both edges registers ( ,
PORTFIO_BOTH
, and ) let the interrupt request generate on
PORTGIO_BOTH PORTHIO_BOTH
both edges.
The GPIO polarity registers are used to configure the polarity of the
GPIO input source. To select active high or rising edge, set the bits in the
GPIO polarity register to 0. To select active low or falling edge, set the
bits in the GPIO polarity register to 1. This register has no effect on
GPIOs that are defined as outputs. The contents of the GPIO polarity
registers are cleared at reset, defaulting to active high polarity.
The GPIO interrupt sensitivity registers are used to configure each of the
inputs as either a level-sensitive or an edge-sensitive source. When using
an edge-sensitive mode, an edge detection circuit is used to prevent a situ-
ation where a short event is missed because of the system clock rate. The
GPIO interrupt sensitivity register has no effect on GPIOs that are
defined as outputs. The contents of the GPIO interrupt sensitivity regis-
ters are cleared at reset, defaulting to level sensitivity.
The GPIO set on both edges registers are used to enable interrupt genera-
tion on both rising and falling edges. When a given GPIO has been set to
edge-sensitive in the GPIO interrupt sensitivity register, setting the
respective bit in the GPIO set on both edges register to both edges results
in an interrupt being generated on both the rising and falling edges. This
register has no effect on GPIOs that are defined as level-sensitive or as
outputs. See Table 9-4 on page 9-14 for information on how the GPIO
set on both edges register interacts with the GPIO polarity and GPIO
interrupt sensitivity registers.
ADSP-BF50x Blackfin Processor Hardware Reference 9-17