Ppi Delay Count Register (Ppi_Delay) - Analog Devices ADSP-BF506F Hardware Reference Manual

PPI Registers

PPI Delay Count Register (PPI_DELAY)

The
PPI_DELAY
urations except ITU-R 656 modes and GP modes with 0 frame syncs. It
contains a count of how many
before starting to read in or write out data.
PPI_FS1

Note in TX modes using at least one frame sync, there is a
one-cycle delay beyond what is specified in the
PPI Delay Count Register (PPI_DELAY)
15 14 13 12 11 10
0 0 0 0
Figure 20-15. PPI Delay Count Register
PPI Transfer Count Register (PPI_COUNT)
The
PPI_COUNT
except "RX mode with 0 frame syncs, external trigger" and "TX mode
with 0 frame syncs." For RX modes, this register holds the number of sam-
ples to read into the PPI per line, minus one. For TX modes, it holds the
number of samples to write out through the PPI per line, minus one. The
register itself does not actually decrement with each transfer. Thus, at the
beginning of a new line of data, there is no need to rewrite the value of
this register. For example, to receive or transmit 100 samples through the
PPI, set
PPI_COUNT
20-32
register, shown in
PPI_CLK
9 8 7 6 5 4
0 0 0 0 0 0 0 0
register, shown in
to 99.
ADSP-BF50x Blackfin Processor Hardware Reference
Figure 20-15, can be used in all config-
cycles to delay after assertion of
3 2 1 0
Reset = 0x0000
0 0 0 0
PPI_DELAY[15:0]
Number of PPI_CLK cycles to
delay after assertion of
PPI_FS1 before latching in or
sending out data
Figure 20-16, is used in all modes
register.
PPI_DELAY