Interrupt Output - Analog Devices ADSP-BF506F Hardware Reference Manual

clock phase relative to data are programmable in the
define the transfer format. See

Interrupt Output

The SPI has two interrupt output signals: a data interrupt and an error
interrupt.
The behavior of the SPI data interrupt signal depends on the
in the
SPI_CTL
acts as a DMA request and is generated when the DMA FIFO is ready to
be written to (
mode ( =
TIMOD
ter is ready to be written to (
is ready to be read from (
An SPI error interrupt is generated in a master when a mode fault error
occurs, in both DMA and non-DMA modes. An error interrupt can also
be generated in DMA mode when there is an underflow (
= ) or an overflow (
TIMOD b#11
In non-DMA mode, the underflow and overflow conditions set the
and bits in the
RBSY
error interrupt.
For more information about this interrupt output, see the discussion of
the bits in
TIMOD
Functional Description
The following sections describe the functional operation of the SPI.
ADSP-BF50x Blackfin Processor Hardware Reference
Figure 18-5 on page
register. In DMA mode (
= ) or read from (
TIMOD b#11
), a data interrupt is generated when the
0X
TIMOD
=
TIMOD
RBSY
register, respectively, but do not generate an
SPI_STAT
"SPI Control (SPI_CTL) Register" on page
SPI-Compatible Port Controller
=
TIMOD b#1X
=
TIMOD b#10
= ) or when the
b#01
).
b#00
when =
TIMOD b#10
register and
SPI_CTL
18-13.
field
TIMOD
), the data interrupt
). In non-DMA
regis-
SPI_TDBR
register
SPI_RDBR
when
TXE
) error condition.
TXE
18-36.
18-17