Analog Devices ADSP-BF506F Hardware Reference Manual page 400

Description of Operation
When the GPIO's input drivers are enabled while the GPIO direction reg-
isters configure it as an output, software can trigger a GPIO interrupt by
writing to the data/set/toggle registers. The interrupt service routine
should clear the GPIO to acknowledge the request.
Each of the three GPIO modules provides two independent interrupt
channels. Identical in functionality, these are called interrupt A and inter-
rupt B. Both interrupt channels have their own mask register which lets
you assign the individual GPIOs to none, either, or both interrupt
channels.
Since all mask registers reset to zero, none of the GPIOs is assigned any
interrupt by default. Each GPIO represents a bit in each of these registers.
Setting a bit means enabling the interrupt on this channel.
Interrupt A and interrupt B operate independently. For example, writing
1 to a bit in the mask interrupt A register does not affect interrupt channel
B. This facility allows GPIOs to generate GPIO interrupt A, GPIO inter-
rupt B, both GPIO interrupts A and B, or neither.
A GPIO interrupt is generated by a logical OR of all unmasked GPIOs for
that interrupt. For example, if
interrupt channel A, GPIO interrupt A will be generated when triggered
by or . The interrupt service routine must evaluate the GPIO data
PF0 PF1
register to determine the signaling interrupt source.
the interrupt flow of any GPIO module's interrupt A channel.

When using either rising or falling edge-triggered interrupts, the
interrupt condition must be cleared each time a corresponding
interrupt is serviced by writing 1 to the appropriate bit in the
GPIO clear register.
At reset, all interrupts are masked and disabled.
9-18
and
PF0
ADSP-BF50x Blackfin Processor Hardware Reference
are both unmasked for GPIO
PF1
Figure 9-1 illustrates