Analog Devices ADSP-BF506F Hardware Reference Manual page 462

Timer Registers
Timer Disable Register (TIMER_DISABLE)
15 14 13 12 11 10
0 0 0
TIMDIS7 (Timer7 Disable)
1 - Disable timer
Read as 1 if this timer is enabled
TIMDIS6 (Timer6 Disable)
1 - Disable timer
Read as 1 if this timer is enabled
TIMDIS5 (Timer5 Disable)
1 - Disable timer
Read as 1 if this timer is enabled
TIMDIS4 (Timer4 Disable)
1 - Disable timer
Read as 1 if this timer is enabled
This diagram shows an example configuration for eight timers. Differ-
ent products have different numbers of timers.
Figure 10-17. Timer Disable Register
In mode, a write of a "1" to
PWM_OUT
responding timer immediately. Rather, the timer continues running and
stops cleanly at the end of the current period (if
(if
PERIOD_CNT
mode to stop immediately by first writing a "1" to the corre-
PWM_OUT
sponding bit in
corresponding
PWM_OUT Mode" on page
In and
WDTH_CAP
the corresponding timer immediately.
10-38
9 8 7 6
0 0 0 0 0 0 0
= 0). If necessary, the processor can force a timer in
, and then writing a "1" to the
TIMER_DISABLE
bit in
TRUN TIMER_STATUS
10-22.
modes, a write of a "1" to
EXT_CLK
ADSP-BF50x Blackfin Processor Hardware Reference
5 4 3 2 1 0
0 0 0 0 0 0 Reset = 0x0000
TIMDIS0 (Timer0 Disable)
1 - Disable timer
Read as 1 if this timer is enabled
TIMDIS1 (Timer1 Disable)
1 - Disable timer
Read as 1 if this timer is enabled
TIMDIS2 (Timer2 Disable)
1 - Disable timer
Read as 1 if this timer is enabled
TIMDIS3 (Timer3 Disable)
1 - Disable timer
Read as 1 if this timer is enabled
TIMER_DISABLE
PERIOD_CNT
. See "Stopping the Timer in
does not stop the cor-
= 1) or pulse
stops
TIMER_DISABLE