Parallel Peripheral Interface - Analog Devices ADSP-BF506F Hardware Reference Manual

Parallel Peripheral Interface

The six PWM output signals in each PWM controller consist of three
high-side drive signals (
drive signals (
PWM_AL
PWM signal can be set with software, so that either active high or active
low PWM patterns can be produced. The switching frequency of the gen-
erated PWM pattern is programmable. The PWM generator can operate
in single update mode or double update mode. In single update mode the
duty cycle values are programmable only once per PWM period, so that
the resultant PWM patterns are symmetrical about the midpoint of the
PWM period. In the double update mode, a second updating of the PWM
registers is implemented at the midpoint of the PWM period. In this
mode, it is possible to produce asymmetrical PWM patterns that produce
lower harmonic distortion in 3-phase PWM inverters.
Parallel Peripheral Interface
The processor provides a Parallel Peripheral Interface (PPI) that can con-
nect directly to parallel A/D and D/A converters, ITU-R 601/656 video
encoders and decoders, and other general-purpose peripherals. The PPI
consists of a dedicated input clock pin and three multiplexed frame sync
pins. The input clock supports parallel data rates up to half the system
clock rate.
In ITU-R 656 modes, the PPI receives and parses a data stream of 8-bit or
10-bit data elements. On-chip decode of embedded preamble control and
synchronization information is supported.
1-14
,
PWM_AH PWM_BH
, , and
PWM_BL PWM_CL
ADSP-BF50x Blackfin Processor Hardware Reference
, and ) and three low-side
PWM_CH
). The polarity of the generated