Dma Configuration Registers (Dmax_Config/Mdma_Yy_Config) - Analog Devices ADSP-BF506F Hardware Reference Manual

DMA Registers
DMA Configuration Registers
(DMAx_CONFIG/MDMA_yy_CONFIG)
The DMAx_CONFIG register, shown in
DMA parameters and operating modes. Writing the DMAx_CONFIG
register while DMA is already running will cause a DMA error unless writ-
ing with the DMAEN bit set to 0.

DMA Configuration Registers (DMAx_CONFIG/MDMA_yy_CONFIG)

R/W prior to enabling channel; RO after enabling channel
15 14 13 12 11 10
0 0 0
FLOW[2:0] (Next
Operation)
0x0 - Stop
0x1 - Autobuffer mode
0x4 - Descriptor array
0x6 - Descriptor list (small model)
0x7 - Descriptor list (large model)
NDSIZE[3:0] (Flex Descriptor Size)
Size of next descriptor
0000 - Required if in Stop or Autobuffer mode
0001 - 1001 - Descriptor size
1010 - 1111 - Reserved
DI_EN (Data Interrupt Enable)
0 - Do not allow completion of
work unit to generate an interrupt
1 - Allow completion of work unit
to generate a data interrupt
DI_SEL (Data Interrupt Timing Select)
Applies only when DMA2D = 1
0 - Interrupt after completing
whole buffer (outer loop)
1 - Interrupt after completing
each row (inner loop)
Figure 7-6. DMA Configuration Registers
7-68
9 8 7 6 5
0 0 0 0 0 0 0 0
ADSP-BF50x Blackfin Processor Hardware Reference
Figure 7-6, is used to set up
4 3 2 1 0
Reset = 0x0000
0 0 0 0 0
DMAEN (DMA
Channel Enable)
0 - Disable DMA channel
1 - Enable DMA channel
WNR (DMA Direction)
0 - DMA is a memory read
(source) operation
1 - DMA is a memory write
(destination) operation
WDSIZE[1:0] (Transfer
Word Size)
00 - 8-bit transfers
01 - 16-bit transfers
10 - 32-bit transfers
11 - Reserved
DMA2D (DMA Mode)
0 - Linear (One-dimensional)
1 - Two-dimensional (2-D)
SYNC (Work Unit
Transitions)
0 - Continuous transition
1 - Synchronized transition