Dtest_Command Register - Analog Devices ADSP-BF506F Hardware Reference Manual

Processor-Specific MMRs

DTEST_COMMAND Register

When the data test command register (
L1 cache data or tag arrays are accessed, and the data is transferred
through the data test data registers (
shown in Figure
Data Test Command Register (DTEST_COMMAND)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0xFFE0 0300
X
Access Way/Instruction
Address Bit 11
0 - Access Way0/Instruction bit 11 = 0
1 - Access Way1/Instruction bit 11 = 1
Data/Instruction Access
0 - Access Data
1 - Access Instruction
15 14 13 12 11 10
X
Data Cache Select/
Address Bit 14
0 - Reserved when bit 24=0
1 - Select Data Cache Bank when bit 24=1
Set Index[5:0]
Selects one of 64 sets
Double Word Index[1:0]
Selects one of four 64-bit
double words in a 256-bit line
Figure 2-3. Data Test Command Register
The data/instruction access bit allows direct access via the
MMR to L1 instruction SRAM.
Note that
ITEST_COMMAND
from 0xFA00 4000 to 0xFFA0 7FFF.
2-6
2-3.
X X X X X X X X
9 8 7
X X X X X X X X
must be used to access to L1 Instruction SRAM
ADSP-BF50x Blackfin Processor Hardware Reference
DTEST_COMMAND
). This register is
DTEST DATA[1:0]
X X X X X X X
6 5 4 3 2 1 0
X X X X X X X
Read/Write Access
0 - Read access
1 - Write access
Array Access
0 - Access tag array
1 - Access data array
) is written to, the
Reset = Undefined
Subbank Access[1:0]
(SRAM ADDR[13:12])
00 - Access subbank 0
01 - Access subbank 1
10 - Access subbank 2
11 - Access subbank 3
DTEST_COMMAND