Unique Information For The Adsp-Bf50X Processor; Interfaces - Analog Devices ADSP-BF506F Hardware Reference Manual

instructions only, two
clear command and the RTI instruction. However, one
is typically sufficient if the clear command performs in the very beginning
of the service routine, or the
of instructions before the service routine returns. Commonly, a pop-mul-
tiple instruction is used for this purpose as shown in
The level-sensitive nature of peripheral interrupts enables more than one
of them to share the same IVG channel and therefore the same interrupt
priority. This is programmable using the assignment registers. Then a
common service routine typically interrogates the
determine the signalling interrupt source. If multiple peripherals are
requesting interrupts at the same time, it is up to the service routine to
either service all requests in a single pass or to service them one by one. If
only one request is serviced and the respective request is cleared by soft-
ware before the RTI instruction executes, the same service routine is
invoked another time because the second request is still pending. While
the first approach may require fewer cycles to service both requests, the
second approach enables higher priority requests to be serviced more
quickly in a non-nested interrupt system setup.
Unique Information for the ADSP-BF50x
Processor
This section describes
unique to the ADSP-BF50x processor.

Interfaces

Figure 4-3 and
peripheral interrupt request lines connect to the SIC. These figures show
how the seven
able peripheral request inputs of the CEC.
ADSP-BF50x Blackfin Processor Hardware Reference
instructions are recommended between the
SSYNC
SSYNC
Interfaces and
Figure 4-4 provide an overview of how the individual
registers control the assignment to the nine avail-
SIC_IAR
System Interrupts
instruction is followed by another set
Listing
SIC_ISR
System Peripheral Interrupts
instruction
SSYNC
4-1.
register to
that are
4-15