Analog Devices ADSP-BF506F Hardware Reference Manual page 430

Description of Operation
Figure 10-2 shows the interrupt structure of the timers.
ILLEGAL
TIMER_WIDTH
ILLEGAL
TIMER _PERIOD
COUNTER
OVERFLOW
PWM_OUT
TMODE
RESET
MMR WRITE TO
TIMER_STATUS
TOVF_ERR WRITE DATA
Figure 10-2. Timers Interrupt Structure
To enable interrupt generation, set the
rupt source in the
10-6
PERIOD_CNT
WDTH_CAP EXT_CLK
TMODE
ERROR EVENT
IRQ_ENA
SET
TOVF_ERR
RST
and
IMASK SIC_IMASK
ADSP-BF50x Blackfin Processor Hardware Reference
COUNT = WIDTH
COUNT = PERIOD
TRAILING
EDGE
LEADING
EDGE
1
1 0
PWM_OUT WDTH_CAP
INTERRUPT
EVENT
PWM_OUT
SET
TIMER
IRQ
TIMIL
RST
TIMIL WRITE DATA
bit and unmask the inter-
IRQ_ENA
registers. To poll the
0
EXT_CLK
SYSTEM
PROCESSOR
INTERRUPT
CORE
CONTROLLER
bit
TIMIL