Sport Transmit And Receive Frame Sync Divider (Sport_Tfsdiv And Sport_Rfsdiv) Registers - Analog Devices ADSP-BF506F Hardware Reference Manual

SPORT Registers
SPORT Receive Serial Clock Divider Register (SPORT_RCLKDIV)
15 14 13 12 11 10
0 0 0 0 0
Figure 19-35. SPORT Receive Serial Clock Divider Register
SPORT Transmit and Receive Frame Sync Divider
(SPORT_TFSDIV and SPORT_RFSDIV) Registers
The 16-bit SPORT_TFSDIV and SPORT_RFSDIV registers specify how
many transmit or receive clock cycles are counted before generating a TFS
or RFS pulse when the frame sync is internally generated. In this way, a
frame sync can be used to initiate periodic transfers. The counting of serial
clock cycles applies to either internally or externally generated serial
clocks. These registers are shown in
SPORT Transmit Frame Sync Divider Register (SPORT_TFSDIV)
15 14 13 12 11 10
0 0 0 0 0
Figure 19-36. SPORT Transmit Frame Sync Divider Register
19-64
9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
9 8 7 6 5 4 3
0 0 0 0 0 0 0 0
ADSP-BF50x Blackfin Processor Hardware Reference
2 1 0
0 0 0 Reset = 0x0000
Serial Clock Divide
Modulus[15:0]
Figure 19-36 and
2 1 0
Reset = 0x0000
0 0 0
Frame Sync Divider[15:0]
Number of transmit clock cycles
counted before generating TFS pulse
Figure 19-37.