Rsi Interface Configuration - Analog Devices ADSP-BF506F Hardware Reference Manual

Functional Description
The output is enabled or disabled via the
RSI_CLK
RSI_CLK_CONTROL
that allows for the disabling of the
PWR_SV_EN
are no transfers taking place on the RSI interface.

RSI Interface Configuration

The RSI supports multiple card types via the various protocols. Different
card types may require slightly different interface configurations.
The command signal on MMC cards operates in two different modes
depending on the cards operating mode. During the card identification
mode, this signal operates in open-drain configuration, however upon the
cards entry to data transfer mode, the signal is then configured to
push-pull mode. The internal pull-up resistor of the
intended to keep the signal from floating. The internal pull-up resistor is
not sufficient during the card identification phase when the MMC card
signal is operating in open-drain mode. If support for MMC
RSI_CMD
devices is required, an external pull-up resistor should be added to the
signal as detailed in the JEDEC standard. The bus width used for
SD_CMD
the data transfers is configurable to 1-bit, 4-bits, or 8-bits via the
field in the
RSI_CLK_CONTROL
(RSI_CLK_CONTROL)" on page
21-10
= ---------------------------------------------- -
RSI_CLK
 
2
register and a power save feature is implemented via
register (see
21-55).
ADSP-BF50x Blackfin Processor Hardware Reference
SCLK

+
CLKDIV 1
CLK_EN
RSI_CLK
RSI_CMD
"RSI Clock Control Register
bit in the
output when there
signal is only
BUS_MODE