Analog Devices ADSP-BF506F Hardware Reference Manual page 628

UART Registers
content of receive shift register
occurs. The
OE
UART Line Status Registers (UARTx_LSR)
15 14 13 12 11 10
For memory-
0
mapped
addresses,
see Table 15-7.
TFI (Transmission Finished Indicator) - W1C
0 - TEMT did not transition from 0 to 1
1 - TEMT transition from 0 to 1
TEMT (TSR and UARTx_THR Empty) - RO
0 - Full
1 - Both empty
THRE (THR Empty) - RO
0 - THR not empty
1 - THR empty
BI (Break Interrupt) - W1C
0 - No break interrupt
1 - Break interrupt; this
indicates UARTxRX was
held low for more than the max-
imum word length
Figure 15-10. UART Line Status Registers
Table 15-7. UART Line Status Register Memory-Mapped Addresses
Register Name
UART0_LSR
UART1_LSR
The (parity error) bit indicates that the received parity bit does not
PE
match the expected value. The
bit, that is, by the time the first stop bit is received or when data is
DR
loaded from the receive FIFO to the
and can be cleared by W1C operations. Invalid parity bits can be simu-
lated by setting the
15-34
RSR
bit is sticky and can be cleared by W1C operations.
9 8 7
0 0 0 0 0 0 0 0
Memory-Mapped Address
0xFFC0 0414
0xFFC0 2014
PE
bit in the
FPE
ADSP-BF50x Blackfin Processor Hardware Reference
, however, is lost as soon as the overrun
6 5 4 3 2 1 0
0 0 0 0 0 0 0
bit is updated simultaneously with the
register. The bit is sticky
UARTx_RBR
register.
UARTx_GCTL
Reset = 0x0060
DR (Data Ready) - RO
0 - No new data
1 - UARTx_RBR holds
new data
OE (Overrun Error) - W1C
0 - No overrun
1 - Overrun error. Read
buffers not overwritten.
PE (Parity Error) - W1C
0 - No parity error
1 - Parity error
FE (Framing Error) - W1C
0 - No error
1 - Invalid stop bit error