Analog Devices ADSP-BF506F Hardware Reference Manual page 629

The (framing error) bit indicates that the first stop bit is sampled. The
FE
bit is updated simultaneously with the
FE
first stop bit is received or when data is loaded from the receive FIFO to
the
UARTx_RBR
ations. Invalid stop bits can be simulated by setting the
register.
UARTx_GCTL
The (break indicator) bit indicates that the first stop bit is sampled low
BI
and the entire data word, including parity bit, consists of low bits only.
The bit is updated simultaneously with the
BI
the first stop bit is received or when data is loaded from the receive FIFO
to the
UARTx_RBR
operations.
The (transmit hold register empty) bit indicates that the UART
THRE
transmit channel is ready for new data and software can write to
. Writes to
THR
passed from
UARTx_THR
The (transmitter empty) bit indicates that both the
TEMT
ter and the internal
permitted to write to the
The bit can also be used as indicator that pending UART transmis-
TEMT
sion is completed. At that time it is safe to disable the
three-state the off-chip line driver.
The (transmission finished indicator) bit is a sticky version of the
TFI
bit. While
TEMT
written to the
cleared by software (W1C). The
interrupt timing.
ADSP-BF50x Blackfin Processor Hardware Reference
register. The bit is sticky and can be cleared by W1C oper-
register. The bit is sticky and can be cleared by W1C
clear the
UARTx_THR
to the internal
register are empty. In this case the program is
TSR
UARTx_THR
is automatically cleared by hardware when new data is
register, the sticky
UARTx_THR
UART Port Controllers
bit, that is, by the time the
DR
bit, that is, by the time
DR
bit. It is set again when data is
THRE
register.
TSR
register twice without losing data.
bit remains set until it is
TFI
bit enables more flexible transmit
TFI
bit in the
FFE
UARTx_
regis-
UARTx_THR
bit or to
UCEN
TEMT
15-35