Interface Overview - Analog Devices ADSP-BF506F Hardware Reference Manual

Interface Overview

Figure 20-1 shows a block diagram of the PPI.
PAB
DMA
CONTROLLER
DAB
Figure 20-1. PPI Block Diagram
The pin accepts an external clock input. It cannot source a clock
PPI_CLK
internally.

When the
latency cycles before data gets received or transmitted. In RX and
TX modes, there may be at least 2 cycles latency before valid data is
received or transmitted.
The not only supplies the PPI module itself, but it also can clock
PPI_CLK
one or more GP Timers to work synchronously with the PPI. Depending
on PPI operation mode, the
input. For more information, see the General-Purpose Timers chapter.
ADSP-BF50x Blackfin Processor Hardware Reference
PPI_CONTROL
PPI_COUNT
PPI_STATUS
PPI_DELAY
PPI_FRAME
16 BITS
*
PACK/
16-DEEP
UNPACK
FIFO
is not free-running, there may be additional
PPI_CLK
PPI_CLK
Parallel Peripheral Interface
SYNC
GATE
can either equal or invert the
PPI_CLK
DATA BUS
FS1
FS2
FS3
TMRCLK
20-3