Data Output Configuration Bit (Cr9) - Analog Devices ADSP-BF506F Hardware Reference Manual

Command Interface to Internal Flash Memory

Data Output Configuration Bit (CR9)

The data output configuration bit determines whether the output remains
valid for one or two clock cycles. When the data output configuration bit
is '0' the output data is valid for one clock cycle. When the data output
configuration bit is '1' the output data is valid for two clock cycles.
The data output configuration depends on the condition:
where t is the clock period, t
K
the system that is accessing the flash (for example, the processor) and t
is the clock to data valid time. If this condition is not satisfied, the data
output configuration bit should be set to '1' (two clock cycles). Refer to
Figure 6-3.
1st CYCLE
K
E
L
A20-A0
VALID ADDRESS
D15-D0
Note: The settings shown are X latency = 4, data output held for one clock cycle.
Figure 6-3. X Latency and Data Output Configuration Example
6-26

+
t t
K KQV
QVK_CPU
X LATENCY
2nd CYCLE 3rd CYCLE 4th CYCLE
ADSP-BF50x Blackfin Processor Hardware Reference
t
QVK_CPU
is the data setup time required by
t
QVK_CPU
VALID DATA
KQV
t
K
t
KQV
VALID DATA