Analog Devices ADSP-BF506F Hardware Reference Manual page 911

SPORT Receive Configuration 1 Register (SPORT_RCR1)
15 14 13 12 11 10
0
RCKFE (Clock Falling
Edge Select)
0 - Drive internal frame sync
on rising edge of RSCLK.
Sample data and external
frame sync with falling
edge of RSCLK.
1 - Drive internal frame sync
on falling edge of RSCLK.
Sample data and external
frame sync with rising
edge of RSCLK.
LARFS (Late Receive
Frame Sync)
0 - Early frame syncs
1 - Late frame syncs
LRFS (Low Receive Frame
Sync Select)
0 - Active high RFS
1 - Active low RFS
RFSR (Receive Frame Sync
Required Select)
0 - Does not require RFS for
every data word
1 - Requires RFS for every data
word
Figure 19-27. SPORT Receive Configuration 1 Register
When the SPORT is enabled to receive (
SPORT configuration register writes are not allowed except for
SPORT_RCLKDIV
disallowed registers have no effect. While the SPORT is enabled,
is not written except for bit 0 (
SPORT_RCR1
write (SPORT_RCR1, 0x0001) ;
write (SPORT_RCR1, 0xFF01) ;
write (SPORT_RCR1, 0xFFF0) ;
ADSP-BF50x Blackfin Processor Hardware Reference
9 8 7
0 0 0 0 0 0 0 0
and multichannel mode channel select registers. Writes to
6 5 4 3 2 1 0
0 0 0 0 0 0 0
set), corresponding
RSPEN
). For example,
RSPEN
/* SPORT RX Enabled */
/* ignored, no effect */
/* SPORT disabled, SPORT_RCR1
still equal to 0x0000 */
SPORT Controller
Reset = 0x0000
RSPEN (Receive Enable)
0 - Receive disabled
1 - Receive enabled
IRCLK (Internal Receive
Clock Select)
0 -External receive clock
selected
1 - Internal receive clock
selected
RDTYPE[1:0] (Data
Formatting Type Select)
00 - Zero fill
01 - Sign-extend
10 - Compand using -law
11 - Compand using A-law
RLSBIT (Receive Bit Order)
0 - Receive MSB first
1 - Receive LSB first
IRFS (Internal Receive Frame
Sync Select)
0 - External RFS used
1 - Internal RFS used
19-53